Test RWC+dmb+rfiar-addrrna

ARM RWC+dmb+rfiar-addrrna
"Rfe DMBdRR FreNaA RfiAR DpAddrdRRNa Fre"
Cycle=RfiAR DpAddrdRRNa Fre Rfe DMBdRR FreNaA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=Rfe DMBdRR FreNaA RfiAR DpAddrdRRNa Fre
{ ok=1;
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1           | P2                  ;
 MOV R0,#1    | LDR R0,[%x1] | MOV %T3,#1          ;
 STR R0,[%x0] | DMB          | LDREX R0,[%y2]      ;
              | LDR R1,[%y1] | STREX %T2,%T3,[%y2] ;
              |              | CMP %T2,#0          ;
              |              | BNE Fail2           ;
              |              | LDREX R1,[%y2]      ;
              |              | EOR R2,R1,R1        ;
              |              | LDR R3,[R2,%x2]     ;
              |              | B Exit2             ;
              |              | Fail2:              ;
              |              | MOV R4,#0           ;
              |              | STR R4,[%ok2]       ;
              |              | Exit2:              ;
Observed
    1:R0=1; 1:R1=0; 2:R0=0; 2:R1=1; 2:R3=0; ok=1; y=1;