Test RWC+ctrlisbrna+dmbnaa+A

ARM RWC+ctrlisbrna+dmbnaa+A
"RfeAR DpCtrlIsbdRRNa Fre DMBdWRNaA FreAA"
Cycle=RfeAR DpCtrlIsbdRRNa Fre DMBdWRNaA FreAA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeAR DpCtrlIsbdRRNa Fre DMBdWRNaA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1             | P2                 ;
 MOV %T3,#1          | LDREX R0,[%x1] | MOV R0,#1          ;
 LDREX R0,[%x0]      | CMP R0,R0      | STR R0,[%y2]       ;
 STREX %T2,%T3,[%x0] | BNE LC00       | DMB                ;
 CMP %T2,#0          | LC00:          | LDREX R1,[%x2]     ;
 BNE Fail0           | ISB            | STREX %T2,R1,[%x2] ;
 B Exit0             | LDR R1,[%y1]   | CMP %T2,#0         ;
 Fail0:              |                | BNE Fail2          ;
 MOV R1,#0           |                | B Exit2            ;
 STR R1,[%ok0]       |                | Fail2:             ;
 Exit0:              |                | MOV R2,#0          ;
                     |                | STR R2,[%ok2]      ;
                     |                | Exit2:             ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R1=0; ok=0; x=1;