Test RWC+addr+dmbaa+A

ARM RWC+addr+dmbaa+A
"RfeANa DpAddrdR FreNaA DMBdWRAA FreAA"
Cycle=RfeANa DpAddrdR FreNaA DMBdWRAA FreAA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeANa DpAddrdR FreNaA DMBdWRAA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1              | P2                  ;
 MOV %T3,#1          | LDR R0,[%x1]    | MOV %T3,#1          ;
 LDREX R0,[%x0]      | EOR R1,R0,R0    | LDREX R0,[%y2]      ;
 STREX %T2,%T3,[%x0] | LDR R2,[R1,%y1] | STREX %T2,%T3,[%y2] ;
 CMP %T2,#0          |                 | CMP %T2,#0          ;
 BNE Fail0           |                 | BNE Fail2           ;
 B Exit0             |                 | DMB                 ;
 Fail0:              |                 | LDREX R1,[%x2]      ;
 MOV R1,#0           |                 | STREX %T2,R1,[%x2]  ;
 STR R1,[%ok0]       |                 | CMP %T2,#0          ;
 Exit0:              |                 | BNE Fail2           ;
                     |                 | B Exit2             ;
                     |                 | Fail2:              ;
                     |                 | MOV R2,#0           ;
                     |                 | STR R2,[%ok2]       ;
                     |                 | Exit2:              ;
Observed
    0:R0=0; 1:R0=1; 1:R2=0; 2:R0=0; 2:R1=0; ok=0; x=1; y=1;