Test WWC+dmbnaa+pora

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=2 ; ok=1 ; x=1 ; y=1"

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=2 ; y=1"

Executions for behaviour: "1:R0=2 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=2 ; y=1"

ARM WWC+dmbnaa+pora
"Rfe DMBdRWNaA RfeAR PodRWRA WseANa"
Cycle=Rfe DMBdRWNaA RfeAR PodRWRA WseANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=Rfe DMBdRWNaA RfeAR PodRWRA WseANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                  | P2                  ;
 MOV R0,#2    | LDR R0,[%x1]        | LDREX R0,[%y2]      ;
 STR R0,[%x0] | DMB                 | MOV %T3,#1          ;
              | MOV %T3,#1          | LDREX R1,[%x2]      ;
              | LDREX R1,[%y1]      | STREX %T2,%T3,[%x2] ;
              | STREX %T2,%T3,[%y1] | CMP %T2,#0          ;
              | CMP %T2,#0          | BNE Fail2           ;
              | BNE Fail1           | B Exit2             ;
              | B Exit1             | Fail2:              ;
              | Fail1:              | MOV R2,#0           ;
              | MOV R2,#0           | STR R2,[%ok2]       ;
              | STR R2,[%ok1]       | Exit2:              ;
              | Exit1:              |                     ;
Observed
    1:R0=1; 1:R1=0; 2:R0=1; 2:R1=2; ok=1; x=1; y=1;
and 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=2; y=1;
and 1:R0=2; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=2; y=1;