Test WWC+addrana+pora+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=0 ; x=1"

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=0 ; x=1"

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=2 ; ok=1 ; x=1"

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=2"

ARM WWC+addrana+pora+A
"RfeAA DpAddrdWANa RfeNaR PodRWRA WseAA"
Cycle=RfeNaR PodRWRA WseAA RfeAA DpAddrdWANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=RfeAA DpAddrdWANa RfeNaR PodRWRA WseAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                 | P2                  ;
 MOV %T3,#2          | LDREX R0,[%x1]     | LDREX R0,[%y2]      ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | MOV %T3,#1          ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | LDREX R1,[%x2]      ;
 CMP %T2,#0          | BNE Fail1          | STREX %T2,%T3,[%x2] ;
 BNE Fail0           | EOR R1,R0,R0       | CMP %T2,#0          ;
 B Exit0             | MOV R2,#1          | BNE Fail2           ;
 Fail0:              | STR R2,[R1,%y1]    | B Exit2             ;
 MOV R1,#0           | B Exit1            | Fail2:              ;
 STR R1,[%ok0]       | Fail1:             | MOV R2,#0           ;
 Exit0:              | MOV R3,#0          | STR R2,[%ok2]       ;
                     | STR R3,[%ok1]      | Exit2:              ;
                     | Exit1:             |                     ;
Observed
    0:R0=0; 1:R0=1; 2:R0=1; 2:R1=0; ok=0; x=1;
and 0:R0=1; 1:R0=1; 2:R0=1; 2:R1=0; ok=0; x=1;
and 0:R0=0; 1:R0=1; 2:R0=1; 2:R1=2; ok=1; x=1;
and 0:R0=1; 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=2;