Test S+dmbnaa+pora

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 1:R1=0 ; ok=0 ; x=2 ; y=1"

Executions for behaviour: "0:R1=0 ; 1:R0=1 ; 1:R1=0 ; ok=1 ; x=2 ; y=1"

ARM S+dmbnaa+pora
"DMBdWWNaA RfeAR PodRWRA WseANa"
Cycle=RfeAR PodRWRA WseANa DMBdWWNaA
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWWNaA RfeAR PodRWRA WseANa
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                  ;
 MOV R0,#2           | LDREX R0,[%y1]      ;
 STR R0,[%x0]        | MOV %T3,#1          ;
 DMB                 | LDREX R1,[%x1]      ;
 MOV %T3,#1          | STREX %T2,%T3,[%x1] ;
 LDREX R1,[%y0]      | CMP %T2,#0          ;
 STREX %T2,%T3,[%y0] | BNE Fail1           ;
 CMP %T2,#0          | B Exit1             ;
 BNE Fail0           | Fail1:              ;
 B Exit0             | MOV R2,#0           ;
 Fail0:              | STR R2,[%ok1]       ;
 MOV R2,#0           | Exit1:              ;
 STR R2,[%ok0]       |                     ;
 Exit0:              |                     ;
Observed
    0:R1=0; 1:R0=1; 1:R1=0; ok=0; x=2; y=1;
and 0:R1=0; 1:R0=1; 1:R1=0; ok=1; x=2; y=1;