Test LB+ctrlisbana+pora

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 1:R1=0 ; ok=1 ; x=1"

ARM LB+ctrlisbana+pora
"DpCtrlIsbdWANa RfeNaR PodRWRA RfeAA"
Cycle=RfeNaR PodRWRA RfeAA DpCtrlIsbdWANa
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpCtrlIsbdWANa RfeNaR PodRWRA RfeAA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                 | P1                  ;
 LDREX R0,[%x0]     | LDREX R0,[%y1]      ;
 STREX %T2,R0,[%x0] | MOV %T3,#1          ;
 CMP %T2,#0         | LDREX R1,[%x1]      ;
 BNE Fail0          | STREX %T2,%T3,[%x1] ;
 CMP R0,R0          | CMP %T2,#0          ;
 BNE LC00           | BNE Fail1           ;
 LC00:              | B Exit1             ;
 ISB                | Fail1:              ;
 MOV R1,#1          | MOV R2,#0           ;
 STR R1,[%y0]       | STR R2,[%ok1]       ;
 B Exit0            | Exit1:              ;
 Fail0:             |                     ;
 MOV R2,#0          |                     ;
 STR R2,[%ok0]      |                     ;
 Exit0:             |                     ;
Observed
    0:R0=1; 1:R0=1; 1:R1=0; ok=1; x=1;