Test LB+addr+pora

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 1:R1=0 ; ok=1 ; x=1"

ARM LB+addr+pora
"DpAddrdW RfeNaR PodRWRA RfeANa"
Cycle=RfeNaR PodRWRA RfeANa DpAddrdW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Rf
Orig=DpAddrdW RfeNaR PodRWRA RfeANa
{ ok=1;
%x0=x; %y0=y;
%y1=y; %x1=x; %ok1=ok;
}
 P0              | P1                  ;
 LDR R0,[%x0]    | LDREX R0,[%y1]      ;
 EOR R1,R0,R0    | MOV %T3,#1          ;
 MOV R2,#1       | LDREX R1,[%x1]      ;
 STR R2,[R1,%y0] | STREX %T2,%T3,[%x1] ;
                 | CMP %T2,#0          ;
                 | BNE Fail1           ;
                 | B Exit1             ;
                 | Fail1:              ;
                 | MOV R2,#0           ;
                 | STR R2,[%ok1]       ;
                 | Exit1:              ;
Observed
    0:R0=1; 1:R0=1; 1:R1=0; ok=1; x=1;