Test WWC+syncaa+pora+A

Executions for behaviour: "1:r1=1 ; 2:r1=1 ; ok=0 ; x=1"

Executions for behaviour: "1:r1=1 ; 2:r1=1 ; ok=1 ; x=1"

Executions for behaviour: "1:r1=1 ; 2:r1=1 ; ok=1 ; x=2"

Executions for behaviour: "1:r1=2 ; 2:r1=1 ; ok=1 ; x=2"

PPC WWC+syncaa+pora+A
"RfeAA SyncdRWAA RfeAR PodRWRA WseAA"
Cycle=RfeAA SyncdRWAA RfeAR PodRWRA WseAA
Prefetch=0:x=F,2:x=W
Com=Rf Rf Ws
Orig=RfeAA SyncdRWAA RfeAR PodRWRA WseAA
{ ok=1;
0:r2=x; 0:r4=ok;
1:r2=x; 1:r4=y; 1:r6=ok;
2:r2=y; 2:r4=x; 2:r6=ok;
}
 P0               | P1               | P2               ;
 li r1,2          | lwarx r1,r0,r2   | lwarx r1,r0,r2   ;
 lwarx %sta,r0,r2 | stwcx. r1,r0,r2  | li r3,1          ;
 stwcx. r1,r0,r2  | bne  Fail1       | lwarx %sta,r0,r4 ;
 bne  Fail0       | sync             | stwcx. r3,r0,r4  ;
 b   Exit0        | li r3,1          | bne  Fail2       ;
 Fail0:           | lwarx %sta,r0,r4 | b   Exit2        ;
 li r3,0          | stwcx. r3,r0,r4  | Fail2:           ;
 stw r3,0(r4)     | bne  Fail1       | li r5,0          ;
 Exit0:           | b   Exit1        | stw r5,0(r6)     ;
                  | Fail1:           | Exit2:           ;
                  | li r5,0          |                  ;
                  | stw r5,0(r6)     |                  ;
                  | Exit1:           |                  ;
Observed
    1:r1=1; 2:r1=1; ok=0; x=1;
and 1:r1=1; 2:r1=1; ok=1; x=1;
and 1:r1=1; 2:r1=1; ok=1; x=2;
and 1:r1=2; 2:r1=1; ok=1; x=2;