Test WWC+pora+syncaa+A

Executions for behaviour: "1:r1=1 ; 2:r1=1 ; ok=0 ; x=1"

Executions for behaviour: "1:r1=1 ; 2:r1=1 ; ok=1 ; x=1"

Executions for behaviour: "1:r1=1 ; 2:r1=1 ; ok=1 ; x=2"

Executions for behaviour: "1:r1=2 ; 2:r1=1 ; ok=1 ; x=2"

PPC WWC+pora+syncaa+A
"RfeAR PodRWRA RfeAA SyncdRWAA WseAA"
Cycle=RfeAA SyncdRWAA WseAA RfeAR PodRWRA
Prefetch=0:x=F,2:x=W
Com=Rf Rf Ws
Orig=RfeAR PodRWRA RfeAA SyncdRWAA WseAA
{ ok=1;
0:r2=x; 0:r4=ok;
1:r2=x; 1:r4=y; 1:r6=ok;
2:r2=y; 2:r4=x; 2:r6=ok;
}
 P0               | P1               | P2               ;
 li r1,2          | lwarx r1,r0,r2   | lwarx r1,r0,r2   ;
 lwarx %sta,r0,r2 | li r3,1          | stwcx. r1,r0,r2  ;
 stwcx. r1,r0,r2  | lwarx %sta,r0,r4 | bne  Fail2       ;
 bne  Fail0       | stwcx. r3,r0,r4  | sync             ;
 b   Exit0        | bne  Fail1       | li r3,1          ;
 Fail0:           | b   Exit1        | lwarx %sta,r0,r4 ;
 li r3,0          | Fail1:           | stwcx. r3,r0,r4  ;
 stw r3,0(r4)     | li r5,0          | bne  Fail2       ;
 Exit0:           | stw r5,0(r6)     | b   Exit2        ;
                  | Exit1:           | Fail2:           ;
                  |                  | li r5,0          ;
                  |                  | stw r5,0(r6)     ;
                  |                  | Exit2:           ;
Observed
    1:r1=1; 2:r1=1; ok=0; x=1;
and 1:r1=1; 2:r1=1; ok=1; x=1;
and 1:r1=1; 2:r1=1; ok=1; x=2;
and 1:r1=2; 2:r1=1; ok=1; x=2;