Test LB+ctrlisyncra+isyncra

Executions for behaviour: "0:r1=1 ; 1:r1=1 ; ok=1"

PPC LB+ctrlisyncra+isyncra
"DpCtrlIsyncdWRA RfeAR ISyncdRWRA RfeAR"
Cycle=RfeAR ISyncdRWRA RfeAR DpCtrlIsyncdWRA
Prefetch=
Com=Rf Rf
Orig=DpCtrlIsyncdWRA RfeAR ISyncdRWRA RfeAR
{ ok=1;
0:r2=x; 0:r4=y; 0:r6=ok;
1:r2=y; 1:r4=x; 1:r6=ok;
}
 P0               | P1               ;
 lwarx r1,r0,r2   | lwarx r1,r0,r2   ;
 cmpw r1,r1       | isync            ;
 beq  LC00        | li r3,1          ;
 LC00:            | lwarx %sta,r0,r4 ;
 isync            | stwcx. r3,r0,r4  ;
 li r3,1          | bne  Fail1       ;
 lwarx %sta,r0,r4 | b   Exit1        ;
 stwcx. r3,r0,r4  | Fail1:           ;
 bne  Fail0       | li r5,0          ;
 b   Exit0        | stw r5,0(r6)     ;
 Fail0:           | Exit1:           ;
 li r5,0          |                  ;
 stw r5,0(r6)     |                  ;
 Exit0:           |                  ;
Observed
    0:r1=1; 1:r1=1; ok=1;