Address and data dependencies |
This note illustrates that address and data dependencies may behave differently. It is reminded that an address dependency occurs when the effective address of a store depends upon the value read by a previous load instruction; while a data dependency occurs when the the value stored by a store instruction depends upon the value. The difference is observable on ARM hardware only, as the tests derive from the LB and S+ffence+po idioms, which are not observed on Power.
Kind | Model | ARM | Relax-Addr-PoR | Tegra2 | APQ8060 | A5X | A6X | Exynos5250 | Tegra3 | Exynos4412 | Exynos5410 | APQ8064 | |
S+dmb+po | Allow | Allow | Ok, 13M/33G | Allow | Ok, 16k/400M | Ok, 13/780M | Ok, 2.7M/2.4G | No, 0/8.6G | No, 0/8.3G | Ok, 302k/860M | Ok, 10M/2.0G | No, 0/6.8G | Ok, 3.8k/800M |
Allow unseen | Allow unseen | Allow unseen | |||||||||||
DataRW | Allow | Allow | Ok, 20k/39G | Allow | No, 0/400M | No, 0/4.5G | Ok, 12k/2.4G | No, 0/8.6G | No, 0/8.3G | No, 0/860M | Ok, 7.4k/2.0G | No, 0/6.8G | Ok, 367/2.8G |
Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | ||||||||
AddrRW | Forbid | Forbid | Ok, 0/61G | Forbid | Ok, 0/1.8G | Ok, 0/4.5G | Ok, 0/5.6G | Ok, 0/8.6G | Ok, 0/8.3G | Ok, 0/5.8G | Ok, 0/13G | Ok, 0/6.8G | Ok, 0/4.9G |
DataWW | Allow | Allow | Ok, 95k/39G | Allow | No, 0/400M | No, 0/4.5G | Ok, 29k/2.4G | No, 0/8.6G | No, 0/8.3G | No, 0/860M | Ok, 63k/2.0G | No, 0/6.8G | Ok, 2.8k/2.8G |
Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | ||||||||
AddrWW | Forbid | Forbid | Ok, 0/61G | Forbid | Ok, 0/1.8G | Ok, 0/4.5G | Ok, 0/5.6G | Ok, 0/8.6G | Ok, 0/8.3G | Ok, 0/5.8G | Ok, 0/13G | Ok, 0/6.8G | Ok, 0/4.9G |
LB | Allow | Allow | Ok, 87M/35G | Allow | Ok, 48k/400M | Ok, 3.7k/780M | Ok, 31M/3.2G | No, 0/9.4G | No, 0/8.3G | Ok, 17M/860M | Ok, 39M/2.0G | No, 0/6.8G | Ok, 231k/800M |
Allow unseen | Allow unseen | Allow unseen | |||||||||||
LB+datas+WW | Allow | Allow | Ok, 649k/46G | Allow | No, 0/400M | No, 0/5.1G | Ok, 182k/3.2G | No, 0/9.4G | No, 0/8.3G | Ok, 332k/2.1G | Ok, 43k/2.0G | No, 0/8.0G | Ok, 92k/6.0G |
Allow unseen | Allow unseen | Allow unseen | Allow unseen | Allow unseen | |||||||||
LB+addrs+RW | Forbid | Forbid | Ok, 0/63G | Forbid | Ok, 0/1.8G | Ok, 0/4.5G | Ok, 0/6.4G | Ok, 0/9.4G | Ok, 0/8.3G | Ok, 0/5.8G | Ok, 0/13G | Ok, 0/6.8G | Ok, 0/4.9G |
LB+addrs+WW | Forbid | Forbid | Ok, 0/63G | Forbid | Ok, 0/1.8G | Ok, 0/4.5G | Ok, 0/6.4G | Ok, 0/9.4G | Ok, 0/8.3G | Ok, 0/5.8G | Ok, 0/13G | Ok, 0/6.8G | Ok, 0/4.9G |
The above table lists some tests that differ only in some dependencies from one load to one store: the dependency being either an address dependency or a data dependency. Names should help to identify the matching tests. For instance LB+addrs+WW matches LB+datas+WW.
Then, one sees that tests with a data dependency are allowed by the model and observed on hardware; while tests with an address dependency are forbidden by the model and not observed on hardware.
Kind | Model | Power | PowerG5 | Power6 | Power7 | |
S+sync+po | Allow | Allow | No, 0/89G | No, 0/6.2G | No, 0/4.1G | No, 0/57G |
Allow unseen | Allow unseen | Allow unseen | Allow unseen | |||
DataRW | Allow | Allow | No, 0/76G | No, 0/5.9G | — | No, 0/48G |
Allow unseen | Allow unseen | Allow unseen | ||||
AddrRW | Forbid | Forbid | Ok, 0/76G | Ok, 0/5.9G | — | Ok, 0/48G |
DataWW | Allow | Allow | No, 0/76G | No, 0/5.9G | — | No, 0/48G |
Allow unseen | Allow unseen | Allow unseen | ||||
AddrWW | Forbid | Forbid | Ok, 0/76G | Ok, 0/5.9G | — | Ok, 0/48G |
LB | Allow | Allow | No, 0/91G | No, 0/6.4G | No, 0/4.0G | No, 0/59G |
Allow unseen | Allow unseen | Allow unseen | Allow unseen | |||
LB+datas+WW | Allow | Allow | No, 0/76G | No, 0/5.9G | — | No, 0/48G |
Allow unseen | Allow unseen | Allow unseen | ||||
LB+addrs+RW | Forbid | Forbid | Ok, 0/75G | Ok, 0/5.9G | — | Ok, 0/48G |
LB+addrs+WW | Forbid | Forbid | Ok, 0/76G | Ok, 0/5.9G | — | Ok, 0/48G |
This document was translated from LATEX by HEVEA.