Test MP+PPO960

PPC MP+PPO960
"Fre LwSyncdWW Rfe DpCtrldW PosWR PosRR DpCtrldW PosWR PosRR"
Cycle=Rfe DpCtrldW PosWR PosRR DpCtrldW PosWR PosRR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpCtrldW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpCtrldW PosWR PosRR DpCtrldW PosWR PosRR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r8=x;
}
 P0           | P1            ;
 li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | cmpw r1,r1    ;
 lwsync       | beq  LC00     ;
 li r3,1      | LC00:         ;
 stw r3,0(r4) | li r3,1       ;
              | stw r3,0(r4)  ;
              | lwz r5,0(r4)  ;
              | lwz r6,0(r4)  ;
              | cmpw r6,r6    ;
              | beq  LC01     ;
              | LC01:         ;
              | li r7,1       ;
              | stw r7,0(r8)  ;
              | lwz r9,0(r8)  ;
              | lwz r10,0(r8) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r10=1)