Test MP+PPO936

PPC MP+PPO936
"Fre LwSyncdWW Rfe DpCtrldW PosWR DpAddrdR DpCtrldW PosWR PosRR"
Cycle=Rfe DpCtrldW PosWR DpAddrdR DpCtrldW PosWR PosRR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdR DpCtrldW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpCtrldW PosWR DpAddrdR DpCtrldW PosWR PosRR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r8=a; 1:r10=x;
}
 P0           | P1             ;
 li r1,2      | lwz r1,0(r2)   ;
 stw r1,0(r2) | cmpw r1,r1     ;
 lwsync       | beq  LC00      ;
 li r3,1      | LC00:          ;
 stw r3,0(r4) | li r3,1        ;
              | stw r3,0(r4)   ;
              | lwz r5,0(r4)   ;
              | xor r6,r5,r5   ;
              | lwzx r7,r6,r8  ;
              | cmpw r7,r7     ;
              | beq  LC01      ;
              | LC01:          ;
              | li r9,1        ;
              | stw r9,0(r10)  ;
              | lwz r11,0(r10) ;
              | lwz r12,0(r10) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r12=1)