PPC WRC+ctrlaa+ctrlisyncaa+A "RfeAA DpCtrldWAA RfeAA DpCtrlIsyncdRAA FreAA" Cycle=RfeAA DpCtrldWAA RfeAA DpCtrlIsyncdRAA FreAA Prefetch=0:x=T,2:x=T Com=Rf Rf Fr Orig=RfeAA DpCtrldWAA RfeAA DpCtrlIsyncdRAA FreAA { ok=1; 0:r2=x; 0:r4=ok; 1:r2=x; 1:r4=y; 1:r6=ok; 2:r2=y; 2:r4=x; 2:r6=ok; } P0 | P1 | P2 ; li r1,1 | lwarx r1,r0,r2 | lwarx r1,r0,r2 ; lwarx %sta,r0,r2 | stwcx. r1,r0,r2 | stwcx. r1,r0,r2 ; stwcx. r1,r0,r2 | bne Fail1 | bne Fail2 ; bne Fail0 | cmpw r1,r1 | cmpw r1,r1 ; b Exit0 | beq LC00 | beq LC01 ; Fail0: | LC00: | LC01: ; li r3,0 | li r3,1 | isync ; stw r3,0(r4) | lwarx %sta,r0,r4 | lwarx r3,r0,r4 ; Exit0: | stwcx. r3,r0,r4 | stwcx. r3,r0,r4 ; | bne Fail1 | bne Fail2 ; | b Exit1 | b Exit2 ; | Fail1: | Fail2: ; | li r5,0 | li r5,0 ; | stw r5,0(r6) | stw r5,0(r6) ; | Exit1: | Exit2: ; exists (ok=1 /\ 1:r1=1 /\ 2:r1=1 /\ 2:r3=0)