Test WRC+po+ctrlisync+A

PPC WRC+po+ctrlisync+A
"RfeAP PodRW Rfe DpCtrlIsyncdR FrePA"
Cycle=RfeAP PodRW Rfe DpCtrlIsyncdR FrePA
Prefetch=0:x=T,2:x=T
Com=Rf Rf Fr
Orig=RfeAP PodRW Rfe DpCtrlIsyncdR FrePA
{ ok=1;
0:r2=x; 0:r4=ok;
1:r2=x; 1:r4=y;
2:r2=y; 2:r4=x;
}
 P0               | P1           | P2           ;
 li r1,1          | lwz r1,0(r2) | lwz r1,0(r2) ;
 lwarx %sta,r0,r2 | li r3,1      | cmpw r1,r1   ;
 stwcx. r1,r0,r2  | stw r3,0(r4) | beq  LC00    ;
 bne  Fail0       |              | LC00:        ;
 b   Exit0        |              | isync        ;
 Fail0:           |              | lwz r3,0(r4) ;
 li r3,0          |              |              ;
 stw r3,0(r4)     |              |              ;
 Exit0:           |              |              ;
exists
(ok=1 /\ 1:r1=1 /\ 2:r1=1 /\ 2:r3=0)