Test WRC+addr+lwsyncpr

PPC WRC+addr+lwsyncpr
"Rfe DpAddrdW Rfe LwSyncdRRPR FreRP"
Cycle=Rfe LwSyncdRRPR FreRP Rfe DpAddrdW
Prefetch=0:x=T,2:x=T
Com=Rf Rf Fr
Orig=Rfe DpAddrdW Rfe LwSyncdRRPR FreRP
{
0:r2=x;
1:r2=x; 1:r5=y;
2:r2=y; 2:r4=x;
}
 P0           | P1            | P2             ;
 li r1,1      | lwz r1,0(r2)  | lwz r1,0(r2)   ;
 stw r1,0(r2) | xor r3,r1,r1  | lwsync         ;
              | li r4,1       | lwarx r3,r0,r4 ;
              | stwx r4,r3,r5 |                ;
exists
(1:r1=1 /\ 2:r1=1 /\ 2:r3=0)