Test WRC+addr+ctrlisyncra

PPC WRC+addr+ctrlisyncra
"Rfe DpAddrdW RfePR DpCtrlIsyncdRRA FreAP"
Cycle=Rfe DpAddrdW RfePR DpCtrlIsyncdRRA FreAP
Prefetch=0:x=T,2:x=T
Com=Rf Rf Fr
Orig=Rfe DpAddrdW RfePR DpCtrlIsyncdRRA FreAP
{ ok=1;
0:r2=x;
1:r2=x; 1:r5=y;
2:r2=y; 2:r4=x; 2:r6=ok;
}
 P0           | P1            | P2              ;
 li r1,1      | lwz r1,0(r2)  | lwarx r1,r0,r2  ;
 stw r1,0(r2) | xor r3,r1,r1  | cmpw r1,r1      ;
              | li r4,1       | beq  LC00       ;
              | stwx r4,r3,r5 | LC00:           ;
              |               | isync           ;
              |               | lwarx r3,r0,r4  ;
              |               | stwcx. r3,r0,r4 ;
              |               | bne  Fail2      ;
              |               | b   Exit2       ;
              |               | Fail2:          ;
              |               | li r5,0         ;
              |               | stw r5,0(r6)    ;
              |               | Exit2:          ;
exists
(ok=1 /\ 1:r1=1 /\ 2:r1=1 /\ 2:r3=0)