Test MP+sync+ctrlrr

PPC MP+sync+ctrlrr
"SyncdWW RfePR DpCtrldRRR FreRP"
Cycle=RfePR DpCtrldRRR FreRP SyncdWW
Prefetch=1:x=T
Com=Rf Fr
Orig=SyncdWW RfePR DpCtrldRRR FreRP
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=x;
}
 P0           | P1             ;
 li r1,1      | lwarx r1,r0,r2 ;
 stw r1,0(r2) | cmpw r1,r1     ;
 sync         | beq  LC00      ;
 li r3,1      | LC00:          ;
 stw r3,0(r4) | lwarx r3,r0,r4 ;
exists
(1:r1=1 /\ 1:r3=0)