Test MP+po+ctrlisyncrp

PPC MP+po+ctrlisyncrp
"PodWW RfePR DpCtrlIsyncdRRP Fre"
Cycle=RfePR DpCtrlIsyncdRRP Fre PodWW
Prefetch=1:x=T
Com=Rf Fr
Orig=PodWW RfePR DpCtrlIsyncdRRP Fre
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=x;
}
 P0           | P1             ;
 li r1,1      | lwarx r1,r0,r2 ;
 stw r1,0(r2) | cmpw r1,r1     ;
 li r3,1      | beq  LC00      ;
 stw r3,0(r4) | LC00:          ;
              | isync          ;
              | lwz r3,0(r4)   ;
exists
(1:r1=1 /\ 1:r3=0)