Test MP+lwsyncap+ctrlrr

PPC MP+lwsyncap+ctrlrr
"LwSyncdWWAP RfePR DpCtrldRRR FreRA"
Cycle=RfePR DpCtrldRRR FreRA LwSyncdWWAP
Prefetch=1:x=T
Com=Rf Fr
Orig=LwSyncdWWAP RfePR DpCtrldRRR FreRA
{ ok=1;
0:r2=x; 0:r4=y; 0:r6=ok;
1:r2=y; 1:r4=x;
}
 P0               | P1             ;
 li r1,1          | lwarx r1,r0,r2 ;
 lwarx %sta,r0,r2 | cmpw r1,r1     ;
 stwcx. r1,r0,r2  | beq  LC00      ;
 bne  Fail0       | LC00:          ;
 lwsync           | lwarx r3,r0,r4 ;
 li r3,1          |                ;
 stw r3,0(r4)     |                ;
 b   Exit0        |                ;
 Fail0:           |                ;
 li r5,0          |                ;
 stw r5,0(r6)     |                ;
 Exit0:           |                ;
exists
(ok=1 /\ 1:r1=1 /\ 1:r3=0)