Test IRIW+poaa+addraa+AP

PPC IRIW+poaa+addraa+AP
"RfeAA PodRRAA FreAP RfePA DpAddrdRAA FreAA"
Cycle=RfeAA PodRRAA FreAP RfePA DpAddrdRAA FreAA
Prefetch=0:x=T,1:y=T,2:y=T,3:x=T
Com=Rf Fr Rf Fr
Orig=RfeAA PodRRAA FreAP RfePA DpAddrdRAA FreAA
{ ok=1;
0:r2=x; 0:r4=ok;
1:r2=x; 1:r4=y; 1:r6=ok;
2:r2=y;
3:r2=y; 3:r5=x; 3:r7=ok;
}
 P0               | P1              | P2           | P3              ;
 li r1,1          | lwarx r1,r0,r2  | li r1,1      | lwarx r1,r0,r2  ;
 lwarx %sta,r0,r2 | stwcx. r1,r0,r2 | stw r1,0(r2) | stwcx. r1,r0,r2 ;
 stwcx. r1,r0,r2  | bne  Fail1      |              | bne  Fail3      ;
 bne  Fail0       | lwarx r3,r0,r4  |              | xor r3,r1,r1    ;
 b   Exit0        | stwcx. r3,r0,r4 |              | lwarx r4,r3,r5  ;
 Fail0:           | bne  Fail1      |              | stwcx. r4,r3,r5 ;
 li r3,0          | b   Exit1       |              | bne  Fail3      ;
 stw r3,0(r4)     | Fail1:          |              | b   Exit3       ;
 Exit0:           | li r5,0         |              | Fail3:          ;
                  | stw r5,0(r6)    |              | li r6,0         ;
                  | Exit1:          |              | stw r6,0(r7)    ;
                  |                 |              | Exit3:          ;
exists
(ok=1 /\ 1:r1=1 /\ 1:r3=0 /\ 3:r1=1 /\ 3:r4=0)