Test 4.SB+poaas

PPC 4.SB+poaas
"PodWRAA FreAA PodWRAA FreAA PodWRAA FreAA PodWRAA FreAA"
Prefetch=0:y=T,1:z=T,2:a=T,3:x=T
Com=Fr Fr Fr Fr
Orig=PodWRAA FreAA PodWRAA FreAA PodWRAA FreAA PodWRAA FreAA
{ ok=1;
0:r2=x; 0:r4=y; 0:r6=ok;
1:r2=y; 1:r4=z; 1:r6=ok;
2:r2=z; 2:r4=a; 2:r6=ok;
3:r2=a; 3:r4=x; 3:r6=ok;
}
 P0               | P1               | P2               | P3               ;
 li r1,1          | li r1,1          | li r1,1          | li r1,1          ;
 lwarx %sta,r0,r2 | lwarx %sta,r0,r2 | lwarx %sta,r0,r2 | lwarx %sta,r0,r2 ;
 stwcx. r1,r0,r2  | stwcx. r1,r0,r2  | stwcx. r1,r0,r2  | stwcx. r1,r0,r2  ;
 bne  Fail0       | bne  Fail1       | bne  Fail2       | bne  Fail3       ;
 lwarx r3,r0,r4   | lwarx r3,r0,r4   | lwarx r3,r0,r4   | lwarx r3,r0,r4   ;
 stwcx. r3,r0,r4  | stwcx. r3,r0,r4  | stwcx. r3,r0,r4  | stwcx. r3,r0,r4  ;
 bne  Fail0       | bne  Fail1       | bne  Fail2       | bne  Fail3       ;
 b   Exit0        | b   Exit1        | b   Exit2        | b   Exit3        ;
 Fail0:           | Fail1:           | Fail2:           | Fail3:           ;
 li r5,0          | li r5,0          | li r5,0          | li r5,0          ;
 stw r5,0(r6)     | stw r5,0(r6)     | stw r5,0(r6)     | stw r5,0(r6)     ;
 Exit0:           | Exit1:           | Exit2:           | Exit3:           ;
~exists
(ok=1 /\ 0:r3=0 /\ 1:r3=0 /\ 2:r3=0 /\ 3:r3=0)